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1 ? fn6592.0 isl54302 12v, 1.5 quad spst switch with latched parallel interface the isl54302 is a quad analog bidirectional switch device targeted at industrial applications, including test and measurement equipment. it feat ures low resistance and low leakage along with 12v operation and can be digitally controlled via a latched parallel interface. this parallel interface features a latch input pin that can be used to connect multiple devices into a parallel arrangement. the isl54302 can operate from a single, or split bipolar power supply and has a 3v logi c interface. the isl54302 is specified for use over the -40 c to +85c temperature range and is available in a 20 ld 4x4 qfn pb-free package. table 1 summarizes the performance of this family. pinout isl54302 (20 ld qfn) top view features ? 4 independently controlled spst switches ? on-resistance @ 12v. . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 ? single or split supply voltage operation ?r on flatness. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <1 ?r on matching between channels . . . . . . . . . . . . . . . . . <0.2 ? turn-on/turn-off time . . . . . . . . . . . . . . . . . . . . . . . 25ns/80ns ? switch bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60mhz ? parallel data interface up to 40mhz ? 3v logic interface ? 20 ld qfn package ? pb-free (rohs compliant) related literature ? tb363 ?guidelines for handling and processing moisture sensitive surface mount devices (smds)? ? tb389 ?pcb land pattern and surface mount guidelines for qfn packages? ? an557 ?recommended test procedures for analog switches? isl54302 block diagram table 1. features at a glance configuration quad spst r on 1.5 t on /t off 25ns/80ns package 20 ld qfn 4x4 2b 2a 1b 1a cs-latch nc vss vdd vlogic vplus s1-ctrl s2-ctrl gnd s3-ctrl s4-ctrl 3a 3b 4a 4b nc 1 2 3 4 5 678910 15 14 13 12 11 20 19 18 17 16 ordering information part number (note) part marking temp. range (c) package (pb-free) pkg. dwg. # ISL54302IRZ* 54 302irz -40 to +85 20 ld 4x4 qfn l20.4x4c *add ?-t? for tape and reel. please refer to tb347 for details on reel specifications. note: these intersil pb-free plas tic packaged products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate plus anneal - e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. latches level shifter 1 of 4 vlogic gnd vdd vss sw-a sw-b vplus vss s1-ctrl s2-ctrl s3-ctrl s4-ctrl cs-latch data sheet march 19, 2008 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2008. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 march 19, 2008 pin descriptions pin number pin name pin description 1 2b switch 2 signal terminal 2 2a switch 2 signal terminal 3 1b switch 1 signal terminal 4 1a switch 1 signal terminal 5 cs-latch chip select input 6 s1-ctrl switch one logic control 7 s2-ctrl switch two logic control 8 gnd device ground terminal 9 s3-ctrl switch three logic control 10 s4-ctrl switch four logic control 11 nc not internally connected 12 4b switch 4 signal terminal 13 4a switch 4 signal terminal 14 3b switch 3 signal terminal 15 3a switch 3 signal terminal 16 vplus positive analog power supply 17 vlogic logic supply voltage 18 vdd level shifter supply voltage 19 vss negative analog power supply 20 nc not internally connected isl54302
3 march 19, 2008 absolute maximum rati ngs thermal information vplus to vss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to15v vdd to vss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 5v vlogic to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 5v vss to gnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -4v to 0.3v vplus to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 15v all other pins (note 1) . . . . . . . . ((vss) - 0.3v) to ((vplus) + 0.3v) continuous current (any terminal) . . . . . . . . . . . . . . . . . . . . . 35ma peak current, 1a-4a,1b-4b (pulsed 1ms, 10% duty cycle, max) . . . . . . . . . . . . . . . . . 100ma esd rating human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>3kv cdm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >1.5kv machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300v thermal resistance (typical) ja (c/w) jc (c/w) 20 ld qfn package (notes 2, 3) . . . . . . 32 1.4 maximum junction temperature (plastic package). . . . . . . . +150c maximum storage temperature range . . . . . . . . . . . . -65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp operating conditions analog switch signal range . . . . . . . . vss + 0.5v to vplus - 0.5v temperature range . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +85c caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 1. signals on 1a-4a,1b-4b, exceeding vplus or vss are clamped by internal diodes. data_in, clock_in, cs_latch exceeding vlogic o r vss are clamped by internal diodes. limit fo rward diode current to maximum current ratings. 2. ja is measured in free air with the component mounted on a high ef fective thermal conductivity te st board with ?direct attach? fe atures. see tech brief tb379. 3. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications test conditions: vplus = +9v, vss = -3v supply, vlogic = 3v, vdd = gnd = 0v, v inh = 2.2v, v inl = 0.8v, unless otherwise specified. parameter test conditions temp (c) min (note 9) typ (note 10) max (note 9) units analog switch characteristics on-resistance, r on i com = 10ma, vxa, vxb within analog signal (see figure 4) 25 2.0 full 2.5 r on matching between channels, r on i com = 10ma, vxa, vxb within analog signal range (note 5) 25 0.2 full 0.3 r on flatness, r flat(on) i com = 10ma, vxa, vxb within analog signal range (note 4) 25 0.4 full 0.6 off leakage current, i no(off) vxa, vxb within analog signal range 25 15 na full -200 +200 na digital input characteristics (note 8) input voltage high, digital interface s w-ctrl(1-4), cs_latch full 2.2 1.75 v input voltage low, digital interface sw-ctrl(1-4), cs_latch full 1.75 0.8 v sw-ctrl (1-4) into cs_latch setup time t setup (note 6, figure 5) full 1 ns sw-ctrl (1-4) into cs_latch hold time t hold (note 6, figure 5) full 3.5 ns input current, i inh , i inl v in = 0v or vlogic full -1 0.01 1 a cs_latch rise, fall time 10% to 90% and 90% to 10% full 3 ns cs_latch minimum pulse width rising to falling edge 50% points full 10 ns switch dynamic characteristics turn-on time, t on vxa, vxb = 3v, r l = 300 , c l = 35pf, v in = 0v to 3v, (see figure 1) 25 50 ns full 55 ns isl54302
4 march 19, 2008 turn-off time, t off vxa, vxb = 3v, r l = 300 , c l = 35pf, v in = 0v to 3v, (see figure 1) 25 90 ns full 95 ns off capacitance, c off f = 1mhz, vxa or vxb = 0v 25 50 pf on capacitance, c com(on) f = 1mhz, vxa or vxb = 0v 25 100 pf off isolation r l = 50 , c l = 15pf, f = 1mhz, vxa or vxb = 1v p-p (see figure 3) 25 -45 db crosstalk (note 5) 25 -65 db switch contact 3db bandwidth r l = 50 , c l = 5pf 60 mhz charge injection, q c l = 1nf, v g = 0v, r g = 0 ( see figure 2) 25 125 pc power supply characteristics vplus supply, i (quiescent) 25 15 a full 17 45 a vplus supply, i (40mhz) 25 18 a full 22 a vss supply, i (quiescent) 25 16 a full 22 50 a vss supply, i (40mhz) 25 1 ma full 1 ma vdd supply, i (quiescent) 25 1 a full 4 10 a vdd supply, i (40mhz) 25 0.4 ma full 0.4 ma vlogic internal logic supply, i (quiescent) 25 0 a full 1 10 a vlogic internal logic supply, i (40mhz) 25 3.5 ma full 3.5 ma electrical specifications test conditions: vplus = +7v, vss = 0v supply, vlogic= 3v, vdd = 3v, gnd = 0v, v inh = 2.2v, v inl = 0.8v, unless otherwise specified. parameter test conditions temp (c) min (note 9) typ (note 10) max (note 9) units analog switch characteristics on-resistance, r on i com = 10ma, vxa, vxb within analog signal range (see figure 4) 25 2.7 full 3.5 r on matching between channels, r on i com = 10ma, vxa, vxb within analog signal range (note 5) 25 0.1 full 0.15 r on flatness, r flat(on) i com = 10ma, vxa, vxb within analog signal range (note 4) 25 0.5 full 0.6 off leakage current, i no(off) vxa = 1v, 4.5v, vxb= 4.5v, 1v 25 3 na full -200 30 200 na digital input characteristics (note 8) input voltage high, digital interface s w-ctrl(1-4), cs_latch full 2.2 1.75 v input voltage low, digital interface sw-ctrl(1-4), cs_latch full 1.75 0.8 v electrical specifications test conditions: vplus = +9v, vss = -3v supply, vlogic = 3v, vdd = gnd = 0v, v inh = 2.2v, v inl = 0.8v, unless otherwise specified. (continued) parameter test conditions temp (c) min (note 9) typ (note 10) max (note 9) units isl54302
5 march 19, 2008 sw-ctrl (1-4) into cs_latch setup time t setup (note 6, figure 5) full 1 ns sw-ctrl (1-4) into cs_latch hold time t hold (note 6, figure 5) full 3.5 ns input current, i inh , i inl v in = 0v or vlogic full -1 0.01 1 a cs_latch rise, fall time 10% to 90% and 90% to 10% full 3 ns cs_latch minimum pulse width rising to falling edge 50% points full 10 ns dynamic characteristics turn-on time, t on vxa or vxb = 3v, r l = 300 , c l = 35pf (see figure 1) 25 25 ns full 30 ns turn-off time, t off vxa or vxb = 3v, r l = 300 , c l = 35pf (see figure 1) 25 80 ns full 85 ns off capacitance, c off f = 1mhz, vxa or vxb = v com = 0v 25 50 pf on capacitance, c com(on) f = 1mhz, vxa or vxb = v com = 0v 25 100 pf off isolation r l = 50 , c l = 15pf, f = 1mhz, vxa or vxb= 1v p-p (see figure 3) 25 -45 db crosstalk (note 5) 25 -65 db switch contact 3db bandwidth r l = 50 , c l = 5pf 25 60 mhz charge injection, q c l = 1nf, v g = 0v, r g = 0 ( see figure 2) 25 25 pc power supply characteristics vplus supply, i (quiescent) 25 13 a full 15 45 a vplus supply, i (40mhz) 25 18 a full 20 a vss supply, i (quiescent) 25 14 a full 19 50 a vss supply, i (40mhz) 25 0.7 ma full 0.7 ma vdd supply, i (quiescent) 25 1 a full 4 10 a vdd supply, i (40mhz) 25 0.4 ma full 0.5 ma vlogic internal logic supply, i (quiescent) 25 0 a full 1 10 a vlogic internal logic supply, i (40mhz) 25 3.2 ma full 3.2 ma notes: 4. flatness is defined as the delta between the maximum and minimum r on values over the specified voltage range. 5. between any two switches. 6. cs_latch must remain low when changing sw-ctrl(1-4) condition. likewise, while cs_latch is being toggled, it is important to keep sw- ctrl(1-4) in the intended switch condition. 7. typical values are not production tested 8. digital characteristics remain stable with respect to vplus and vss variation. these parameters are controlled by the differe nce between vss and vdd, which the user should maintain at a constant spread of vdd = vss + 3v. 9. parts are 100% tested at +25c. temperature limits established by characterizati on and are not production tested. 10. limits established by characteri zation and are not production tested. electrical specifications test conditions: vplus = +7v, vss = 0v supply, vlogic= 3v, vdd = 3v, gnd = 0v, v inh = 2.2v, v inl = 0.8v, unless otherwise specified. (continued) parameter test conditions temp (c) min (note 9) typ (note 10) max (note 9) units isl54302
6 march 19, 2008 test circuits and waveforms switch changes state on rising edge of cs-latch. v na = vout at all times. figure 1a. measurement points repeat test for all switches. c l includes fixture and stray capacitance. figure 1b. test circuit figure 1. switching times switch changes state on rising edge of cs-latch. figure 2a. measurement points repeat test for all switches. c l includes fixture and stray capacitance. figure 2b. test circuit figure 2. charge injection repeat test for all switches. figure 3. off isolation test circuit repeat test for all switches. figure 4. r on test circuit 50% t r < 20ns t f < 20ns 75% 3v v nb 0v cs-latch input switch output v out 25% t on t off v out v nb v out v (nb) r l r l r on () + ---------------------------- = switch inputs sx-crtl input v out r l c l 1-4a 1-4b in 300 35pf gnd vss c v nb c latch vplus c vdd c vlogic c v out v out on off on q = v out x c l switch output controller sequence 3v 0v sw: on/off/on c l v out r g v g gnd 1-4a 1-4b vplus c in c vss latch vdd c vlogic c analyzer r l signal generator 1-4a 1-4b gnd c vss cs-latch/sx-crtl vplus c vdd c vlogic c cs-latch/sx-crtl 1-4a 1-4b gnd v xa v 1 r on = v 1 /10ma 10ma c vss vplus c vdd c vlogic c isl54302
7 march 19, 2008 isl54302 detailed description the isl54302 quad analog switches offer switching capability from a split-supply -3v and +9v or single 0v and 5v to 12v supply. please review ?power supply considerations? on page 7 before powering up the device. the user can employ multi-devi ce control data in two ways. the s1-s4-ctrl lines can be connected to several devices, with each device having its own cs-latch connection to the system controller. the other way is to have separate s1-4-ctrl connections for each switch and a single cs-latch connection to all isl54302s. power supply considerations the isl54302 construction consists of cmos analog switches and four supply pins: vplus, vss, vlogic, vdd and gnd. vplus and vss determine the switch voltage range of the four spst cmos s witches and set their analog voltage limits. there are no connections between the switch contact signal path and gnd. vlogic and gnd power the digital input/output logic level shifters (thus setting the digital switching point). the level shifters convert the external logic levels to vdd and vss signals to drive the internal digital circuitry. vdd and vss power the internal logic of the device. vdd must always be held at a fixed 3v above vss to avoid device damage. whether operating split or single device, gnd will always be @ 0v and vlogic will always be @ 3v. vdd should always remain 3v above vss. vss to vplus should not exceed a maximum spread of more than 12v. for examples, see the following: split positive and negative switch range operation ? vss = -3v, vdd = +0v, vplus = +9v, vlogic = 3v ? vss = -1v, vdd = +2v, vplus = +11v, vlogic = 3v positive switch range operation ? vss = 0v, vdd = +3v, vplus = +12v, vlogic = 3v isl54302 paralle l communications the isl54302 operates based on parallel data. ctrl and latch inputs are 3v level compatible. setup and hold times relative to the rising the edge of the cs-latch input must be maintained for proper operat ion. switch control data is clocked into internal registers on the rising edge of cs-latch. multiple device connection the user can configure the four sx-ctrl inputs to connect to several isl54302?s. in this configuration each isl54302 requires a separate/dedicated cs-latch input. therefore, each device will update at different times. so in essence, the s1-s4-ctrl signals are multiplexed and connected to all switch control inputs in parallel (see figure 8). for non-multiplexed connections, each sx-ctrl input must have a dedicated logic input for each switch/each device. if three isl54302s are being used, the user must supply 12 dedicated sx-ctrl signals. all switches are then tied to the same cs-latch pin and all devices would change state at the same time. isl54302 cs-latch pin discussion the isl54302?s operational state does not change while sx-ctrl inputs are changing. the user must insure that the cs-latch pin remains low and does not change state while sx-ctrl inputs are changing. once the user has set the sx-ctrl inputs, the cs-latch pin is then utilized. just as the cs-latch pin must remain low during sx-ctrl setup, th e sx-ctrl pins must remain stable during and after the cs-latch operation. the switch from present to next operation occurs on the rising edge on the cs-latch pin. this rising edge transfers data to the internal 4-bit sw itch control re gisters. this transfer updates opening/closi ng of the four switches. isl54302 power on reset (por) switch conditions are controlled during por (power on reset). during and after a por condition, the switches are opened until closed by the controller. figure 5. setup and hold times test circuits and waveforms (continued) cs-latch input t setup sx-ctrl data = 1 100% 100% data = 0 sx-ctrl should remain in desired st ate, before during and after cs-latch. t hold 50% 50% isl54302
8 march 19, 2008 supply sequencing and overvoltage protection with any cmos device, proper power supply sequencing is required to protect the device from excessive input currents, which might permanently damage the ic. all switch contact i/o pins contain esd protection diodes from the pin to vplus and to vss (see figure 7). to prevent forward biasing these diodes, vplus, gnd and vss must be applied before any input signals, and switch signal voltages must remain between vplus and vss. digital control signals should be limited to vlogic and vss. specific power sequence 1. gnd 2. vss typical . . . . . . . . . . . 3v to 0v with respect to gnd 3. vplus typical . . . . . . . +5v to +9v with respect to gnd 4. vdd . . . . . . . . . . . . . . . . . . . +3v to with respect to vss 5. vlogic . . . . . . . . . . . . . . . . . . +3v with respect to gnd if these conditions cannot be guaranteed, then one of the following two protection methods should be employed. logic inputs can easily be protected by adding a 1k resistor in series with the input. the resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. adding a series resistor to the switch input defeats the purpose of using a low r on switch, so two small signal diodes can be added in series with the supply pins to provide overvoltage protection for all pins (see figure 7). these additional diodes limit the analog signal from 1v below vplus to 1v above vss. the leakage current performance is unaffected by this approach, but the switch resi stance may increase, especially at low supply voltages. esd protection the device contains esd protection on the device pins. these devices are design to work based on dv/dt. during power-up, the user should review the rise/fall times on the power connections. the rise time of the power rails should not be faster than 1s. sw1-a s2-ctrl s1-ctrl s1 control s4-ctrl level shifter s3-ctrl cs-latch sw1-b sw2-a s2 control sw2-b sw3-b s3 control sw3-a sw4-b s4 control sw4-a internal cs-latch registers internal cs-latch registers level shifter level shifter level shifter level shifter figure 6. isl54302 functional diagram figure 7. esd/overvoltage protection clamp vplus vss clamp vdd vss clamp vlogic gnd vplus one for each pin listed: 1a, 1b, 2a, 2b, 3a, 3b, 4a, 4b, vlogic gnd one for each pin listed: s1-ctrl, s2-ctrl, vss vdd, vlogic s3-ctrl, s4-ctrl, cs-latch isl54302
9 march 19, 2008 logic-level thresholds vlogic and gnd power the internal logic level shifter stages, so vplus and vss have no affect on logic thresholds. thus, sx-ctrl, cs-latch receive thresholds which will remain constant, despite changes to vplus and vss. leakage considerations reverse esd protection diodes are internally connected between each analog-signal pin and both vplus and vss. one of these diodes conducts if any analog signal exceeds vplus or vss. isl54302 device programming programming the device entails accessing the internal switch control registers. to wr ite data into the register, the data must be transferred via the cs-latch pin. via the cs-latch pin, the programmer has complete control as to ?when? data is transferred to the internal latches. until such time as the cs-latch pin is ?toggled,? the device will remain as previously programmed. therefore, data transitions on the sx-ctrl inputs will not effect the switch?s operational condition. isl54302
10 march 19, 2008 c7 0.1f c14 0.1f c15 0.1f c16 0.1f gnd c6 0.1f c11 0.1f c12 0.1f c13 0.1f c5 0.1f c8 0.1f c9 0.1f c10 0.1f sw1-ctrl sw2-ctrl cs-latch device 1 c1 4.7f c2 4.7f c3 4.7f c4 4.7f gnd vsub (-3v to 0v) vdd (vsub +3v) vlogic (gnd + 3v) vplus (vsub+5 to vsub+12v) digital inputs from system controller device decoupling switch contact connections switch contact connections switch contact connections switch contact connections sw3-ctrl sw4-ctrl cs-latch device 2 cs-latch device 3 isl54302 isl54302 2b 1 2a 2 1b 3 1a 4 4b 12 4a 13 3a 15 3b 14 sw1_ctrl 6 nc 20 sw2_ctrl 7 vss 19 gnd 8 vdd 18 sw3_ctrl 9 vlogic 17 cs-latch 5 nc 11 vplus 16 sw4_ctrl 10 isl54302 2b 1 2a 2 1b 3 1a 4 4b 12 4a 13 3a 15 3b 14 sw1_ctrl 6 nc 20 sw2_ctrl 7 vss 19 gnd 8 vdd 18 sw3_ctrl 9 vlogic 17 cs-latch 5 nc 11 vplus 16 sw4_ctrl 10 2b 1 2a 2 1b 3 1a 4 4b 12 4a 13 3a 15 3b 14 sw1_ctrl 6 nc 20 sw2_ctrl 7 vss 19 gnd 8 vdd 18 sw3_ctrl 9 vlogic 17 cs-latch 5 nc 11 vplus 16 sw4_ctrl 10 figure 8. isl54302 sw-control lines multiplexed isl54302
11 march 19, 2008 typical performance curves vlogic = 3v, t a = +25c, v ih = 3v, v il = 0v, unless otherwise specified. figure 9. on-resistance vs switch voltage figure 10. on-resistance vs switch voltage figure 11. on-resistance vs switch voltag e figure 12. on-resistance vs switch voltage figure 13. on-resistance vs switch voltag e figure 14. on-resistance vs switch voltage -3 -2 -1 0 1 2 3 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 +85c -40c +25c r on ( ) v com (v) vss = -3v, vplus = 3v, vdd = 0v i com = 10ma 0 12345 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 r on ( ) v com (v) vss = 0v, vplus = 5v , vdd = 3v i com = 10ma +85c -40c +25c -3-2-101234567 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 r on ( ) v com (v) vss = -3v, vplus = 7v , vdd = 0v i com = 10ma +85c -40c +25c 0 1 2 3 4 5 6 7 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 r on ( ) v com (v) vss = 0v, vplus = 7v , vdd = 3v i com = 10ma +85c -40c +25c -3 -2 -1 0 1 2 3 4 5 6 7 8 9 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 r on ( ) v com (v) vss = -3v, vplus = 9v , vdd = 0v i com = 10ma +85c -40c +25c 0123456789101112 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 r on ( ) v com (v) vss = 0v, vplus = 12v , vdd = 3v i com = 10ma +85c -40c +25c isl54302
12 march 19, 2008 figure 15. on-leakage vs switch voltage figure 16. on-leakage vs switch voltage figure 17. on-leakage vs switch voltage f igure 18. on-leakage vs switch voltage figure 19. on-leakage vs switch voltage f igure 20. on-leakage vs switch voltage typical performance curves vlogic = 3v, t a = +25c, v ih = 3v, v il = 0v, unless otherwise specified. (continued) -3 -2 -1 0 1 2 3 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 v com (na) v com (v) vss = -3v, vplus = 3v , vdd = 0v 0 12345 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 v com (na) v com (v) vss = 0v, vplus = 5v , vdd = 3v -3-2-101234567 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 v com (na) v com (v) vss = -3v, vplus = 7v , vdd = 0v 0 1 2 3 4 5 6 7 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 v com (na) v com (v) vss = 0v, vplus = 7v, vdd = 3v -3 -2 -1 0 1 2 3 4 5 6 7 8 9 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 v com (na) v com (v) vss = -3v, vplus = 9v, vdd = 0v 0 1 2 3 4 5 6 7 8 9 10 11 12 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 v com (na) v com (v) vss = 0v, vplus = 12v, vdd = 3v isl54302
13 march 19, 2008 figure 21. off-leakage vs switch voltage figure 22. off-leakage vs switch voltage figure 23. off-leakage vs switch voltage f igure 24. off-leakage vs switch voltage figure 25. off-leakage vs switch voltage f igure 26. off-leakage vs switch voltage typical performance curves vlogic = 3v, t a = +25c, v ih = 3v, v il = 0v, unless otherwise specified. (continued) -3 -2 -1 0 1 2 3 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 v com (na) v com (v) vss = -3v, vplus = 3v, vdd = 0v 0 12345 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 v com (na) v com (v) vss = 0v, vplus = 5v, vdd = 3v -3-2-101234567 10 9 8 7 6 5 4 3 2 1 0 v com (na) v com (v) vss = -3v, vplus = 7v, vdd = 0v 0 1 2 3 4 5 6 7 10 9 8 7 6 5 4 3 2 1 0 v com (na) v com (v) vss = 0v, vplus = 7v, vdd = 3v -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10 9 8 7 6 5 4 3 2 1 0 v com (na) v com (v) vss = -3v, vplus = 9v, vdd = 0v 0 1 2 3 4 5 6 7 8 9 10 11 12 10 9 8 7 6 5 4 3 2 1 0 v com (na) v com (v) vss = 0v, vplus = 12v, vdd = 3v isl54302
14 march 19, 2008 figure 27. on-resistance vs supply voltage figure 28. on-resistance vs supply voltage figure 29. digital switching poin t vs supply voltage figure 30. device quiescent current (vplus) figure 31. charge injection vs switch voltage figure 32. t on vs vcom typical performance curves vlogic = 3v, t a = +25c, v ih = 3v, v il = 0v, unless otherwise specified. (continued) 34567 8 9 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 r on ( ) vplus (v) vss = -3v, vcom = vplus - 1v, vdd = 0v i com = 10ma +85c -40c +25c 3.0 4.5 6.0 7.5 9.0 10.5 12.0 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 r on ( ) vplus (v) vss = 0v, vcom = vplus - 1v, vdd = 3v i com = 10ma +85c -40c +25c 2.5 2.7 2.9 3.1 3.3 3.5 2.00 1.94 1.88 1.82 1.76 1.70 1.64 1.58 1.52 1.46 1.40 v in (v) vplus (v) vss = -3v, vdd = 0v +85c -40c +25c 3 4 56789 17.0 16.5 16.0 15.5 15.0 14.5 14.0 13.5 13.0 12.5 12.0 vplus ( a) vplus (v) vss = -3v, vdd = 0v +85c -40c +25c q (pc) v com (v) 0 50 100 150 200 250 300 350 400 450 -3 -2 -1 10 11 12 789 456 123 0 vplus = 9v, vss = -3v, vdd = 0v vplus = 12v, vss = 0v, vdd = 3v vplus = 7v, vss = 0v, vdd = 3v -3 -2 -1 7 8 9 45 6 123 0 time (ns) v com (v) vplus = 9v, vss = -3v, vdd = 0v vplus = 9v, vss = 0v, vdd = 3v 0 10 20 30 40 50 60 isl54302
15 march 19, 2008 figure 33. crosstalk figure 34. off-isolation figure 35. frequency r esponse figure 36. timing typical performance curves vlogic = 3v, t a = +25c, v ih = 3v, v il = 0v, unless otherwise specified. (continued) frequency (hz) 1k 100k 1m 100m 500m 10k 10m crosstalk -110 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 0 r l = 50 vplus = 9v, vss = 0v, vdd = 3v vplus = 9v, vss = -3v, vdd = 0v frequency (hz) 1k 100k 1m 100m 500m 10k 10m off isolation (db) 110 10 20 30 40 50 60 70 80 90 100 r l = 50 0 vplus = 9v, vss = 0v, vdd = 3v vplus = 9v, vss = -3v, vdd = 0v frequency (mhz) 0 -1 -2 normalized gain (db) gain v ss = -3v, v dd = 0v 1 10 100 600 v in = 0.2v p-p to 2v p-p r l = 50 v ss = 0v, v dd = 3v -3 -4 -5 -6 -7 -8 vplus = 9v 40ms/div 0 4 0 4 0 4 cs-latch vplus = 5v to 9v, vss = 0v, vdd = 3v sx-crtl vout with vcom = 3v data = 1 data = 0 switch on switch off isl54302
16 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com march 19, 2008 l20.4x4c 20 lead quad flat no-lead plastic package rev 0, 11/06 located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" typical recommended land pattern top view bottom view side view 4.00 a 4.00 b 6 pin 1 index area (4x) 0.15 4x 0.50 2.0 16x 20 16 15 11 pin #1 index area 6 2 .70 0 . 15 5 1 20x 0.25 +0.05 / -0.07 0.10 m ab c 20x 0.4 0.10 4 6 10 base plane seating plane 0.10 see detail "x" 0.08 c c c 0 . 90 0 . 1 0 . 2 ref c 0 . 05 max. 0 . 00 min. 5 ( 3. 8 typ ) ( 2. 70 ) ( 20x 0 . 6) ( 20x 0 . 5 ) ( 20x 0 . 25 ) isl54302

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